Mendeley
TY  _  JOUR
ID  -  1401041538387
TI  -  Presenting a Network-on-Chip Mapping Approach Based on Harmony Search Algorithm
JO  -  Nashriyyah -i Muhandisi -i Barq va Muhandisi -i Kampyutar -i Iran
JA  -  ES
LA  -  fa
SN  -  16823745
AU  -  Bagheri Zahra
AU  -  Vardi Fatemeh
AU  -  Mahjoub Alireza
AD  -  دانشگاه آزاد اسلامی واحد پرند
AD  -  دانشگاه آزاد پرند
AD  -  دانشگاه آزاد اسلامی واحد کرج
Y1  -  2023
PY  -  2023
VL  -  2
IS  -  
SP  -  77
EP  -  88
KW  -  Networks on chip
KW  -   mapping
KW  -   harmony search
KW  -   heuristic
DO  -  
N2  -  In network-on-chip implementation, mapping can be considered as an important step in application implementation. The tasks of an application are often represented in the form of a core graph. The cores establish a link between themselves using a communication platform and often the network on the chip. For finding proper mapping for an application, developers have proposed various algorithms. In most cases, due to the complexity, exact search methods are used to find the mapping. However, these methods are suitable for networks with small dimensions. As the size of the network increases, the search time also increases exponentially. This article, from the perspective of a heuristic approach, uses the harmony search method to decide when to connect cores to routers. Our approach uses an improved version of the harmony search algorithm with a focus on reducing power consumption and delay. Algorithm complexity analysis reveals a more appropriate solution compared to similar algorithms with respect to application traffic pattern. Compared to similar methods, the algorithm achieves 39.98% less delay and 61.11% saving in power consumption.
UR  - rimag.ir/en/Article/38387
L1  - rimag.ir/en/Article/Download/38387
ER  -  
