Mendeley
TY  _  JOUR
ID  -  1401101740696
TI  -  Design of New Ternary Flip Flops Using CNTFET in Nanotechnology
JO  -  Nashriyyah -i Muhandisi -i Barq va Muhandisi -i Kampyutar -i Iran
JA  -  ES
LA  -  fa
SN  -  16823745
AU  -  rahbari katayoun
AU  -  hosseinoi seyed ali
AD  -  
AD  -  گروه الکترونیک دانشکده برق دانشگاه ازاد واحد یادگار امام خمینی (ره)/ تهران- ایران
Y1  -  2023
PY  -  2023
VL  -  3
IS  -  
SP  -  167
EP  -  177
KW  -  Flip-flop
KW  -   Ternary Circuits
KW  -   Carbon Nanotube Transistor
DO  -  
N2  -  Using multi-valued logic can reduce chip interconnections, which can have a direct effect on chip area and interconnections power consumption. In recent years, due to the ability of Nano electronics in the design of multi-level circuits, research in this field has flourished.  The sequential circuits, flip-flops are important components of processors and VLSI circuits. In this paper, for the first time, a ternary flip-flop with a pulse generator has been proposed, and also a ternary binary-decode flip-flop and the first flip-flop using a buffer have been introduced. Then these flip-flops are compared with themselves and previous circuits. Also, these flip-flops have been used in the design of the ternary counter. The simulation results with HSPICE software show the correct performance of the proposed circuits. There is a 20% improvement in delay and a reduction in the number of transistors in the STI pulse generator flip-flop model, 30% in the SP flip-flop, and 30% in the buffer flip-flop. Also, in the comparison table, the advantages and disadvantages of each have been examined.
UR  - rimag.ir/en/Article/40696
L1  - rimag.ir/en/Article/Download/40696
ER  -  
